| PAT. NO. | Title | ||
| 1 | 6,125,381 |  |
Recursively partitioned carry select adder |
| 1 | 5,918,075 | |
Access network for addressing subwords in memory for both little and big endian byte order |
| Date | Item |
|---|---|
| 1970/03/03 | born in Stuttgart (Germany) |
| 1976/09/14 | started Primary School in Neubieberg/Munich |
| 1980/09/16 | started Gymnasium in Munich |
| 1989/06/22 | finished Gymnasium with Abitur grade |
| 1989/07/03 | started military substitude service ("Zivildienst") in Martha-Maria hostpital in Munich |
| 1990/09/30 | finished military substitude service |
| 1990/WS | started studies of computer science at Munich University of Technology (Technische Universität München/TUM) |
| 1997/SS | finished studies of computer science at TUM with Diplom (Master of Science) grade |
German, English, French, and a 2 1/2 year course in Chinese
| WWW/News | innd/apache/squid |
|---|---|
| Synthesis | Ambit, Design Compiler, Leonardo |
| Simulation | Modelsim, Affirma, Hsim, Eldo |
| Design Environment | Cadence, Mentor Graphics |
| Years | Project |
|---|---|
| 4 | Development of a Forth compiler system (bigFORTH) on a 68k platform (Atari ST). Generation of peephole-optimizied code. Integrated development environment, featuring decompiler, debugger, assembler, disassembler, support of host OS GUI. Published in VD 3/1991, Bernd Paysan, "Ein optimierender Forth-Compiler" Runs standalone on a 68k VME box, too. |
| 3 | Porting bigFORTH to 386/DOS, other features as above, object oriented extension, text-based GUI library. |
| 5 | Development of a portable free Forth system based on a C-coded engine (GNU Forth, Gforth), written with a loosely-knit team over the internet. Published e.g. in EuroFORTH '93 conference proceedings, M. Anton Ertl, "A portable Forth engine", see also http://www.jwdt.com/~paysan/gforth.html |
| 3 | Design and implementation of a stack-based VLIW processor architecture
especially suited for signal processing, while having low-latency
calls and branches to fit high level language demands. Specifying
the instruction set architecture, development of a simulator and
demo programs, implementation in 12k lines synthesizable Verilog,
performance estimation in 0.35u CMOS: at 300 MHz around 2 GOPS.
Implements functional units, FPU, caches, instruction decoding,
branch unit, bus interface... Started to write a compiler prototype (not finished yet). Diploma Thesis "Implementation of the 4stack processor using Verilog", http://www.jwdt.com/~paysan/4stack.html |
| 2 | Development of a GUI editor and a underlying widget library for bigFORTH. bigFORTH port to Linux and Windows 95/NT. About 100 widget classes. Published in Tagungsband Forth Tagung '97, Bernd Paysan, "MINOS - Visual bigFORTH", published on EuroForth'97, find the paper in http://www.jwdt.com/~paysan/bigforth.html |
| - | b16 scalable minimalistic CPU; USB core, see http://www.b16-cpu.de/ |
| From-To | Employer, Responsibilities |
|---|---|
| 1990/1-now | Own company Software engineer: development of Forth systems, Forth GUIs, part-time job |
| 1997/7-1998/10 | Mixed Mode ASIC Design ASIC Designer: consulting customers in ASIC projects. Wrote a C++ Model for a CAN peripheral for Siemens HL. Wrote tests for the VHDL model of the CAN peripheral. Designed a generic peripheral class, support for event driven C++ hardware simulation library. |
| 1998/10-now | Mikron AG IC Design Engineer:
|
| PAT. NO. | Title | ||
| 1 | 6,125,381 | |
Recursively partitioned carry select adder |
| 1 | 5,918,075 | |
Access network for addressing subwords in memory for both little and big endian byte order |
My main interest goes to the digital side of mixed-signal design, especially in connection with signal processing, with emphasis on a hardware-software codesign.