Live Dates

DateItem
1970/03/03born in Stuttgart (Germany)
1976/09/14started Primary School in Neubieberg/Munich
1980/09/16started Gymnasium in Munich
1989/06/22finished Gymnasium with Abitur grade
1989/07/03started military substitude service ("Zivildienst") in Martha-Maria hostpital in Munich
1990/09/30finished military substitude service
1990/WSstarted studies of computer science at Munich University of Technology (Technische Universität München/TUM)
1997/SSfinished studies of computer science at TUM with Diplom (Master of Science) grade

Knowledge

Languages

German, English, French, and a 2 1/2 year course in Chinese

Programming Languages

Forth, C, Verilog, VHDL, 68k-Assembler, i386-Assembler, PIC17, Lisp/Scheme, C++, Modula-II, Java, Prolog, (La)TeX, HTML, shell scripts

OS (System Programming)

Linux, DOS, Windows 95/NT, Atari TOS, HP-UX

Tools

WWW/Newsinnd/apache/squid
SynthesisAmbit, Design Compiler, Leonardo
SimulationModelsim, Affirma, Hsim, Eldo
Design EnvironmentCadence, Mentor Graphics

Development environments

Emacs/Makefiles, M$ VC++

Projects

YearsProject
4Development of a Forth compiler system (bigFORTH) on a 68k platform (Atari ST). Generation of peephole-optimizied code. Integrated development environment, featuring decompiler, debugger, assembler, disassembler, support of host OS GUI. Published in VD 3/1991, Bernd Paysan, "Ein optimierender Forth-Compiler" Runs standalone on a 68k VME box, too.
3Porting bigFORTH to 386/DOS, other features as above, object oriented extension, text-based GUI library.
5Development of a portable free Forth system based on a C-coded engine (GNU Forth, Gforth), written with a loosely-knit team over the internet. Published e.g. in EuroFORTH '93 conference proceedings, M. Anton Ertl, "A portable Forth engine", see also http://www.jwdt.com/~paysan/gforth.html
3Design and implementation of a stack-based VLIW processor architecture especially suited for signal processing, while having low-latency calls and branches to fit high level language demands. Specifying the instruction set architecture, development of a simulator and demo programs, implementation in 12k lines synthesizable Verilog, performance estimation in 0.35u CMOS: at 300 MHz around 2 GOPS. Implements functional units, FPU, caches, instruction decoding, branch unit, bus interface...
Started to write a compiler prototype (not finished yet).
Diploma Thesis "Implementation of the 4stack processor using Verilog", http://www.jwdt.com/~paysan/4stack.html
2Development of a GUI editor and a underlying widget library for bigFORTH. bigFORTH port to Linux and Windows 95/NT. About 100 widget classes. Published in Tagungsband Forth Tagung '97, Bernd Paysan, "MINOS - Visual bigFORTH", published on EuroForth'97, find the paper in http://www.jwdt.com/~paysan/bigforth.html
-b16 scalable minimalistic CPU; USB core, see http://www.b16-cpu.de/

Employment History

From-ToEmployer, Responsibilities
1990/1-nowOwn company
Software engineer: development of Forth systems, Forth GUIs, part-time job
1997/7-1998/10Mixed Mode ASIC Design
ASIC Designer: consulting customers in ASIC projects. Wrote a C++ Model for a CAN peripheral for Siemens HL. Wrote tests for the VHDL model of the CAN peripheral. Designed a generic peripheral class, support for event driven C++ hardware simulation library.
1998/10-nowMikron AG
IC Design Engineer:
  • Smart Battery Fuel Gauge, third generation: Developed software simulator to develop and debug firmware, participated in firmware development, debugging and prototype evaluation (1 year)
  • Smart Battery Charger: Software simulator and firmware development, participated in SMBus interface development (half a year), redesign of digital part (new timer and watchdog, debugged SMBus) for second release (1/2 year)
  • Smart Battery Fuel Gauge, fourth generation: Software simulator, technical project leader. Integration and debugging of digital part, evaluation and test development (1.5 years).
  • Acoustic Touch Screen: Project leader, digital design (integration of Inventra USB and 8051, flash and SRAM), specification, analog supervision (analog part comprises two PLLs, amplification, bandpass filter, pipelined ADC) (2 years).

US Patents

PAT. NO.Title
1 6,125,381 Recursively partitioned carry select adder
1 5,918,075 Access network for addressing subwords in memory for both little and big endian byte order

Opportunity

My main interest goes to the digital side of mixed-signal design, especially in connection with signal processing, with emphasis on a hardware-software codesign.


Bernd Paysan, 1997-12-30, 1997-12-30