Curriculum Vitae

name	Bernd Paysan
date of birth	1970/03/03
nationality	German

Education

1976-1978	Primary School Neubiberg near Munich
1978-1980	Primary School Samberger Schule in Munich
1980-1989 Abitur	Gymnasium in Pullach/Munich
1990-1997 Diplom	Computer Science at TU München

Alternative Civilian Service

1989-1990	alternative civilian service in Martha-Maria hospital in Munich

Knowledge

Languages

German (mother tong), English (excellent), French (fluent), Chinese (moderate, 2.5 years course, experience during travels)

Programming Languages

Forth, C, Verilog, VHDL, 68k-Assembler, i386-Assembler, PIC17, Lisp/Scheme, C++, Modula-II, Java, Prolog, (La)TeX, HTML, TCL, bash

OS (System Programming)

Linux, DOS, Windows, Atari TOS, HP-UX

Tools

network server	apache, squid, dokuwiki, postfix, dovecot (and more)
RTL synthesis	RTL Compiler, Ambit, Design Compiler, Leonardo, Quartus
HDL Simulation	NC Sim, Modelsim, Affirma, Spectre, Ultrasim, Hsim, Eldo
Design Environment	Cadence 5.x, Mentor Graphics
Layout editor	Cadence Virtuoso & Encounter, Mentor tools

Development environments

Emacs/Makefiles, MS VC++; Version control systems: bzr, subversion, cvs

Projects

Date	Project
1988-1991	Development of a Forth compiler system (bigFORTH) on a 68k platform (Atari ST). Generation of peephole-optimizied code. Integrated development environment, featuring decompiler, debugger, assembler, disassembler, support of host OS GUI. Published in VD 3/1991, Bernd Paysan, "Ein optimierender Forth-Compiler" Runs standalone on a 68k VME box, too.
1991-1994	Porting bigFORTH to 386/DOS, other features as above, object oriented extension, text-based GUI library.
1992-now	Development of a portable free Forth system based on a C-coded engine (GNU Forth, Gforth), written with a loosely-knit team over the internet. Published e.g. in EuroFORTH '93 conference proceedings, M. Anton Ertl, "A portable Forth engine", see also http://www.jwdt.com/~paysan/gforth.html
1994-1997	Design and implementation of a stack-based VLIW processor architecture especially suited for signal processing, while having low-latency calls and branches to fit high level language demands. Specifying the instruction set architecture, development of a simulator and demo programs, implementation in 12k lines synthesizable Verilog, performance estimation in 0.35u CMOS: at 300 MHz around 2 GOPS. Implements functional units, FPU, caches, instruction decoding, branch unit, bus interface... Started to write a compiler prototype (not finished). Diploma Thesis "Implementation of the 4stack processor using Verilog", http://www.jwdt.com/~paysan/4stack.html
1997-now	Development of a GUI editor and a underlying widget library for bigFORTH. bigFORTH port to Linux and Windows 95/NT, licence change to GPL. About 100 widget classes. Published in Tagungsband Forth Tagung '97, Bernd Paysan, "MINOS - Visual bigFORTH", published on EuroForth'97, find the paper in http://www.jwdt.com/~paysan/bigforth.html
2002, 2004	b16 scalable minimalistic CPU; USB core, see http://www.jwdt.com/~paysan/b16.html

Employment History

Date	Employer & Role
1990/1-now	Own company Software engineer: development of Forth systems, Forth GUIs, part-time job, see projects above
1997/7-1998/10	Mixed Mode ASIC Design ASIC Designer: consulting customers in ASIC projects. Wrote a C++ Model for a CAN peripheral for Siemens HL. Wrote tests for the VHDL model of the CAN peripheral. Designed a generic peripheral class, support for event driven C++ hardware simulation library.
1998/10-2005/4	Mikron AG IC Design Engineer: Smart Battery Fuel Gauge, third generation: Developed software simulator to develop and debug firmware, participated in firmware development, debugging and prototype evaluation (1 year) Smart Battery Charger: Software simulator and firmware development, participated in SMBus interface development (half a year), redesign of digital part (newtimer and watchdog, debugged SMBus) for second release (1/2 year) Smart Battery Fuel Gauge, fourth generation: Software simulator, technical project leader. Integration and debugging of digital part, evaluation and test development (1.5 years). Acoustic Touch Screen Controller (IntelliTouch): Project leader, digital design (integration of Inventra USB and 8051, flash and SRAM), specification, analog supervision (analog part comprises two PLLs, amplification, bandpass filter, pipelined ADC) (2 years). Laser barcode reader: Project leader, digital design (integration of b16, RAM, ROM, and SPI interface) (2 years, contunied at Zetex) From 2005 also administration of the Unix/Linux network
2005/4-2008/7	Zetex aquired Mikron AG IC Design Engineer: Direct digital feedback amplifier (DDFA): Project leader of the modulator part. Digital design of I²S input, equalizer DSP, upsampling DSP, volume control; conversion from FPGA tool-based output stage. Implementation of a GUI to operate the device and design filters (3 years). Administration of the Munich Linux network
2008/7-2010/2	Diodes aquired Zetex PLC IC Design Engineer: Gasgauge: Digital design: Integration of b16 CPU, I²C interface, RAM, ROM, SPI for debugging, work on 10 bit ADC, debugger interface for software development and demonstration GUI (1 year) Charger: Intersil 9221/Maxim 8601 clone, analog design: Comparator blocks, power transistors (including layout), architecture, and voltage mode regulator (1 year) Administration of the Munich Linux network
2010/2-today	Dialog aquired power management design team

US Patents

Pat. No.	Title
6,125,381	Recursively partitioned carry select adder
5,918,075	Access network for addressing subwords in memory for both little and big endian byte order

Hobbies

Sports	Cycling, hiking, snorkling, nordic skiing
Books	Fantasy like Terry Pratchett, Harry Potter, Journey to the West
Traveling	Great landscape, e.g. in east Asia
Art	Painting, photographing, writing satires

Look here for more details http://www.jwdt.com/~paysan/hobby.html

Club Activities

2002-now	Director of the Forth-Gesellschaft e.V.

Opportunity

My main interest goes to the digital side of mixed-signal design, especially in connection with signal processing, with emphasis on a hardware-software codesign.